1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, the present invention relates to a non-volatile memory device having a floating gate or a floating carrier trap and a method of fabricating the same.
2. Description of Related Art
As shown in FIG. 1 and FIG. 2, a conventional non-volatile memory cell having a floating gate includes a gate pattern comprised of a floating gate 110a, a gate interlayer dielectric film 118, and a control gate electrode 116 deposited in the stated order. Device isolation films 102 are located in portions of a semiconductor substrate to restrict and define active regions 109. The control gate electrode 116 and the gate interlayer dielectric film 118 extend and cross over the device isolation film 102 and are in contact with adjacent memory cells. The floating gate 110a is disposed between the control gate electrode 1 16 and the active region 109, and a tunnel oxide film 104 is disposed between the floating gate 110a and the active region 109. An impurity diffusion layer 120 is located in the active region in-between control gate electrodes 116. A sidewall spacer 122 may be added to a sidewall of the gate pattern.
As shown in FIG. 2, the floating gate 110a of the conventional non-volatile memory device is comprised of a lower floating gate 106a self-aligned to the device isolation film 102 and an upper floating gate 108a on the lower floating gate 106a. The upper floating gate 108a is extended over or overlapped with the device isolation film 102. This overlapping is meant for enlarging the area of the gate interlayer dielectric film 118 that is disposed between the upper floating gate 108a and the control gate electrode 116 in order to improve a coupling ratio of the non-volatile memory device. However, when the upper floating gate 108a overlaps with the device isolation film 102, while the coupling ratio may be improved, it also leads to a problem in which the cell array area is increased in order to guarantee the spacing in-between the upper floating gates 108a. This also leads to several problems associated with the fabrication processes.
FIGS. 3 to 5 illustrate cross-sectional views of a conventional non-volatile memory device having a floating gate, taken along a direction I–I′ of FIG. 1, showing a conventional process.
Referring to FIG. 3, device isolation films 102 restricting a plurality of active regions 109 are formed on portions of a semiconductor substrate 100, and a tunnel oxide film 104 and a lower conductive film pattern 106 are deposited, respectively, in an active region in-between the device isolation films 102. The device isolation films 102 and the lower conductive film pattern 106 are formed conventionally by using a self-aligned trench isolation technology.
Referring to FIG. 4, an upper conductive film pattern 108 is formed on the lower conductive film pattern 106. As a result, a floating gate pattern 110 comprised of the lower conductive film pattern 106 and the upper conductive film pattern 108 is formed in the active region 109. Edges of the upper conductive film pattern 108 are overlapped with the device isolation film 102, and sidewalls of the upper conductive film pattern 108 are formed with a slope. Next, a gate interlayer dielectric film 112 is conformably formed over the entire surface of the semiconductor substrate 100, and then a gate conductive film 114 is formed over the gate interlayer dielectric film 112.
Referring to FIG. 5, a control gate electrode 116 is formed across the device isolation film 102 and a floating gate 110a in a self-aligned fashion, by sequentially patterning the gate conductive film 114, the gate interlayer dielectric film 112, and the floating gate pattern 110, including the tunnel oxide film 104. A gate interlayer dielectric film pattern 118 is disposed between the floating gate 110a and the control gate electrode 116. In the above step, the sloped sidewalls of the floating gate pattern 110 that overlap with the device isolation film 102 reduce the etching burden at the time the gate interlayer dielectric film 112 is etched. Thus, there is a limit in minimizing the cell area because additional space is required to form the sloped sidewalls of the floating gate pattern 110. Also, there is a problem in that a coupling ratio of the cell may be varied according to a configuration of the floating gate pattern 110.